Saikat Chatterjee

Email: 
Phone: 
+49 (0)521 106-67366
Faculty: 
Faculty of Technology
Project title: 
Resource-efficient Design of Multiprocessor System-On-Chips in Sub-threshold domain
Abstract: 
My current work involves around building a standard cell library where the cells are designed to be operated in sub-threshold domain so as to minimize power consumption. The final system will contain multi-voltage levels since the peripherals need to be maintained at above threshold voltage. As a result I am also working on a robust level shifter design. The whole work is being realized in 28 nm ST FDSOI technology.
Publications: