Guest Talk: Sterpone & Bernadeschi

20. Mai 2015

Luca Sterpone:
Title: Fault Tolerance Design Techniques for SRAM-based FPGAs in
Safety-Critical Applications


Modern high performance or low power FPGAs are build using advanced circuit integrated techniques. While these devices are very advantageous for space and avionics based computing, these high levels of integration make FPGA configuration memory cells more susceptible to Single Cell Upsets (SCUs) and Multi Cell Upsets (MCUs). SCUs and MCUs may drastically limit the capability of specific hardening techniques (e. g. Triple Modular Redundancy (TMR)) used in space-based electronic systems. In this presentation, an overview about the existing hardening methodologies will be given. The presentation will focus on the analysis and hardening of configuration bit upsets in the configuration memory of modern SRAM-based FPGA devices. Innovative placement and routing techniques that were developed in order to mitigate the effects of SCUs and MCUs are presented.


Cinzia Bernardeschi:
Title: Integrated Simulation of Implantable Cardiac Pacemaker Software and
Heart Models


An approach for integrated simulation of pacemaker models and heart models, each developed with the appropriate formalism is presented. Heart models are developed in MathWorks, a powerful tool for the
simulation of complex systems, whereas pacemakers are developed in PVS, a theorem-proving environment enabling both simulation and formal verification of safety requirements. The two tools communicate over a
web-based interface, which makes it possible to integrate the simulation of the MathWorks model of the heart and the PVS model of the pacemaker. We illustrate the architecture developed for the integrated simulation of
the pacemaker-heart system and present an example application for realistic models.